As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. Second, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Third, applying the test data to a large circuit requires an increasingly long test application time. And fourth, present external testing equipment is unable to test such larger circuits at their speed of operation.
Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements such as flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational or a nearly combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing all (or almost all) memory elements are connected into one or more shift registers, as shown in U.S. Pat. No. 4,503,537. A circuit that has been designed for test has two modes of operation: a normal mode and a test, or scan, mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit, or test, responses to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit under test (CUT) works properly.
Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Today, ATPG software tools are so efficient that it is possible to generate test sets (a collection of test patterns) that guarantee almost complete fault coverage of several types of fault models including stuck-at, transition, path delay faults, and bridging faults. Typically, when a particular potential fault in a circuit is targeted by an ATPG tool, only a small number of scan cells, e.g., 2-5%, must be specified to detect the particular fault (deterministically specified cells). The remaining scan cells in the scan chains are filled with random binary values (randomly specified cells). This way the pattern is fully specified, more likely to detect some additional faults, and can be stored on a tester.
In a conventional system for testing digital circuits with scan chains, external automatic testing equipment (ATE) applies a set of fully specified test patterns one by one to a CUT in scan mode via scan chains within the circuit. The circuit is then run in normal mode using the test pattern as input, and the test response to the test pattern is stored in the scan chains. With the circuit again in scan mode, the response is then routed to the ATE, which compares the response with a fault-free reference response, also one by one. For large circuits, this approach becomes infeasible because of large test set sizes and long test application times. It has been reported that the volume of test data can exceed one kilobit per single logic gate in a large design. The significant limitation of this approach is that it requires an expensive, memory-intensive tester and a long test time to test a complex circuit.
These limitations of time and storage can be overcome to some extent by adopting a built-in self-test (BIST) framework as shown in FIG. 1. In BIST, additional on-chip circuitry is included to generate test patterns, evaluate test responses, and control the test. Logic BIST controller 100 tests circuit under test (CUT) 110. Typically, automated testing equipment (ATE) 120 is used together with logic BIST controller 100 during testing. A typical logic BIST controller contains a number of component parts including a scan driver 130 containing a device for generating test pattern data, such as pseudo-random pattern generator (PRPG) 140, a scan monitor 150 containing a multiple input shift register (MISR) 160, a shift counter (not shown), and a pattern counter (not shown). Components of a BIST controller may further include additional components, such as a phase shifter in the scan driver and/or a space compactor in the scan monitor.
PRPG 140 is used to generate the test patterns, instead of having deterministic test patterns. PRPGs typically are implemented as a hardware structure called a linear feedback shift register (LFSR). An LFSR comprises a sequence of chained data memory elements forming a shift register. A given LFSR of length n can be represented by its characteristic polynomial hnxn+ . . . +h1x+h0, where the term hixi refers to the ith flip-flop of the register, such that, if hi=1, then there is a feedback tap taken from this flip-flop. When the proper tap connections are established in accordance with the given polynomial, the combined (added modulo 2) output of each stage is feedback to the first stage of the LFSR. Such an implementation is called type I LFSR or Fibonacci generator. An alternative implementation uses a shift register with XOR gates placed between the LFSR cells. It is called type II LFSR or Galois true divisor. A distinct feature of this configuration is that the output of the last stage of the LFSR is being fed back to those stages, which are indicated by the characteristic polynomial employed. A polynomial which causes an n-bit LFSR to go through all possible 2n−1 nonzero states is called a primitive characteristic polynomial. A corresponding LFSR is often referred to as a maximum-length LFSR, while the resultant output sequence is termed a maximum-length sequence or m-sequence.
The pattern counter controls sequences of test patterns generated by PRPG 140 and applied though scan chains 170, 172 and 174 of CUT 110. To reduce correlation between scan chains 170, 172 and 174 in CUT 110, a phase shifter can be inserted between PRPG 140 and the scan chains. A typical phase shifter consists of exclusive-or (XOR) network employed to avoid shifted versions of the same data in various scan paths.
Test pattern data generated by PRPG 140 is sequentially loaded, or shifted, into scan chains 170, 172 and 174. The shift counter indicates how many shift cycles must be performed before all scan chains in CUT 110 have been filled. As each test data bit is shifted in, the response to a test data bit shifted in during the previous pattern is shifted out of scan chains 170, 172 and 174 and into a MISR 160, or a similar signature generation element, in the scan monitor. MISR 160 compresses the response data into a signature which can be analyzed for errors. The number of inputs to MISR 160 cannot exceed the number of bits in the MISR. A space compactor (not shown) may be used if there are more scan chains in CUT 110 than there are bits in a MISR. The space compactor combines adjoining scan chains using XOR gate structures until the number of space compactor outputs is equal to the number of bits, or stages, in the MISR.
Once a complete load/unload operation has been performed, CUT 110 enters a non-scan mode. A system capture operation can be performed to capture response data. During capture operations, output from the scan chains is not shifted into the MISR, and test patterns are not input to the scan chains. Thus, the MISR and the PRPG are typically placed in a non-functional state during capture operations to avoid timing problems. After capture, the system is ready for the next load/unload operation.
This concurrent load/unload activity causes a potential problem. Although the PRPG and MISR may be reset to known values when the logic BIST controller is reset, the first load/unload cycle causes an unknown and potentially uninitialized state of the scan chains to be passed into the scan monitor and hence the MISR. This causes the MISR to become tainted with unknown data. Previous solutions to this tainting problem included initializing the scan chains to a known state prior to running the BIST session (often referred to as external initialization) or masking the MISR inputs by forcing them to known values (such as all 1s or all 0s) until the first capture operation is complete (often referred to as internal or controller initialization).
Internal initialization, or masking, can be used to force MISR inputs to a known value during a masked initial pattern. The masking process is controlled by a mask control signal. Typically, the mask signal is generated by combinational logic, either by comparing the pattern counter with the known constant value for the first pattern if internal initialization is being performed, or by driving it with a constant “no mask” value if external initialization is being performed. External initialization also can be performed without masking circuitry.
FIG. 2 shows an X-bit MISR 160 containing masking hardware. MISR 160 includes flip-flops 210, 212 and 214, multiplexors 220, 222 and 224, XOR gates 230, 232 and 234, and clock signal 240. Response data from scan chains 170, 172 and 174 in CUT 110 are shifted into MISR 160 via scan out signals 250, 252 and 254. Mask signal 260, which is coupled to inverter 270 and AND gates 280, 282 and 284, masks the inputs to the MISR by driving all MISR inputs low during the first pattern (pc=0) of a test sequence. In such an arrangement, the MISR inputs are not masked after the first pattern.
Other logic BIST controllers have allowed suspending MISR signature generation only during capture operations or after the test responses for the last pattern of a test sequence have been shifted into the MISR. For example, referring to FIG. 2, bist_done signal 290 and capture_operation signal 292 can set (via OR gate 294) multiplexors 220, 222 and 224 such that the signature stored in flip-flops 210, 212 and 214 in the MISR is not changed 1) after the test responses for the last pattern of a test sequence have been shifted into the MISR, or 2) during a capture operation, respectively.
However, such solutions to the tainting problem are unsatisfactory because such solutions do not allow suspending MISR signature generation at any other points. Additionally, current EDA synthesis tools may make masking operations ineffective by performing undesirable logic reduction during circuit optimization.